Raised source/drain (S/D) junctions can provide shallow junctions with low series resistance and the use of raised shallow trench isolation (STI) reduces leakage current through the devices and improves the threshold voltage control.
For example, U.S. Pat. No. 5,915,183 to Gambino et al. describes a process for forming raised source/drain (S/D) junctions using CMP (chemical mechanical polishing) combined with a recess etch of blanket polysilicon. The raised S/D are defined by gate conductors and by raised shallow trench isolation (STI). The process uses a salicide gate conductor, and conventional polysilicon deposition, CMP, and recess steps to form the raised S/D junctions, i.e. form SiN layer; form raised STIs; pattern SiN layer and form gate polysilicon; form raised polysilicon S/D; and form a salicide on the gate polysilicon and raised polysilicon S/D.
U.S. Pat. No. 5,789,792 to Tsutsumi describes a semiconductor device including an element isolating region for isolating a transistor formation region having an MOS transistor from other element formation regions. Two or more raised STI are formed in the element isolating region and are comprised of a first isolating and insulating material. A second insulating material is formed between the raised STI with the upper surfaces of the raised STI and second insulating material being at the same level.
U.S. Pat. No. 5,539,229 to Nobel, Jr. et al. describes a semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures, e.g. STI. A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
U.S. Pat. No. 5,918,131 to Hsu et al. describes a method for forming a shallow trench isolation (STI) structure having sidewall spacers that utilizes the early formation of strong oxide spacers so that for any subsequent pad oxide layer or sacrificial oxide layer removal using a wet etching method, the oxide layer adjacent to the substrate will not be over-etched to form recesses, thereby preventing the lowering of threshold voltage and the induction of a kink effect.
U.S. Pat. No. 5,882,983 to Gardner et al. describes a method for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure.
U.S. Pat. No. 5,721,173 to Yano et al. describes a method of forming a trench isolation structure in which a film is formed of a semiconductor substrate and a trench is formed in the semiconductor substrate through the film. A dielectric material is deposited in the trench and on the film. An etch resistant film is formed on the portions of the dielectric material in the trench and on exposed portions of the film at edge regions of the trench. The dielectric material on the film is selectively removed and the etch resistant film remaining on the dielectric material in the trench is selectively removed.
U.S. Pat. No. 5,786,262 to Jang et al. describes a method of forming a shallow trench isolation using ozone-TEOS as a gap filling material.